CPU Cache Subsystem Senior Design Manager
at Google
Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 15 years of experience in CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including micro-architecture definition and PPA processing. Experience leading and managing teams for modern processor subsystems with high speed, lower power design. Experience with front-end quality checks (e.g., Lint, CDC/RDC). Learn more