Design Technology Co-Optimization Engineer

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 2 years of experience in Physical Design (RTL-to-GDS) or Technology Development, focusing on advanced nodes (e.g., 7nm, 5nm, or below). Experience in scripting and automation using Tcl and Python (or Perl) to manage design sweeps and data extraction. Experience with industry-standard Place and Route (P&R) tools and Static Timing Analysis (STA) tools. Experience in CMOS device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA. Learn more