Senior Packaging Design Engineer, Silicon

Bachelor's degree in Mechanical, Material, Electrical Engineering, Technology, Science, a related field, or equivalent practical experience. 5 years of experience in chip package substrate design using Cadence APD (Allegro Package Designer) or Mentor Expedition with package tape-outs. Experience in chip package substrate layout, design rules/verification, design for manufacturing (DFM) and taping out for production. Experience in mobile SOC package design in the following technologies: FCCSP, Package on Package (PoP), InFO, RDL, IPD, 2.5D/3D, Chiplet. Learn more