TPU PCIe RTL Design Engineer

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in ASIC design, including one project focused on PCIe logic. Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl. Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition. Experience with PCIe protocol layers (e.g., Transaction, Data Link, and Physical) or LTSSM. Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows. Learn more