TPU RTL Design Engineer, Networking, Inter-Chip Interconnects
at Google
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience in high-performance ASIC design. Experience architecting or designing RTL solutions for digital systems. Experience developing networking IP across one or more layers, such as the media access control (MAC), link (L2), or physical (PHY) layers. Experience with high-speed interconnects. Learn more